a question about pins and their resou

Why don't you start with the board schematics?

What board is it?

Unfortunately with Altera kits it's the only reliable source. Their documents and reference manuals can have some mistakes.

Is it the PCI development kit that you have? It is the only one that I see with a EP2C35

Your question is ambiguous.

Many boards have more than one crystal on it. For example, my DE1 board has a 24 Mhz, 27 Mhz, and 50 Mhz crystal on it. They are easily found on the board's schematic.

A pll may be used to multiply or divide any of these clock signals that are fed into the dedicated clock inputs of the FPGA, or they may be used as is.

So the question is what clock are you interested in? The clock that goes to an audio chip, SDRAM, Video controller, NIOS 2's system clock, .....?

Assuming you want to know what the NIOS 2's system clock is, you need to find out what signal drives the signal named "clk" in the system instantiation in the top-level HDL file. If it is the output from a PLL, open up the megawizard and choose this existing PLL, and check the parameters there. You will then find the source clock's frequency and the output frequency.

If your top level module is a Quartus schematic file, the parameters used for the PLL are visible in a table somewhere on the schematic sheet.

You'll find all the documents you need here (http://www.altera.com/products/devkits/altera/kit-nios-2c35.html).

From what I see no the schematic, you have a single 50MHz clock source that is connected to the FPGA on pins P25 (osc_CLK0), AC13 (osc_CLK1), N2 (SRAM_CLKIN) and B13 (SDRAM_CLKIN)