a question about DSP block mapping

Hi,

Sorry for the delay. As I understand it, you have some inquiries related to the S10 DSP block. Please see my responses as following:

1. In figure 1, is there any pipeline register between the Multipliers and Adder?

[CP] For your information, the figure is showing the functional representation of the DSP block. Based on it, there is no pipeline register between multiplier and adder. Sorry for the inconvenience.

2. If our design is "multiplier->register->adder->register", could it be mapped to a dsp block? Would quartus map it to dsp block, and map the register inside our design to 1st pipeline register and 2nd pipeline register in figure 1?

[CP] Since the pipeline registers are before the multiplier, it is rather hard for me to tell if Quartus will map your registers to the pipeline registers. I would recommend you to create simple test design and run through Quartus compilation to verify if your design can be mapped and synthesized implemented per your expectation or not.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin