Forum Discussion
EEren
Occasional Contributor
Occasional ContributorA PLL problem.
I created a new project for MAX10 10M50SAE144I7G and copied a PLL and ADC modules in it. component pll is
port
(
inclk0 : in std_logic := '0';
c0 : out std_logic;
c1 : out std_logic;
c2 ...
lixy
Contributor
ContributorHi EEren,
May I know if this issue has been fixed?
Based on previous information, it looks like we need to check in Quartus RTL or technology map and see where is the other PLL from?
Best Regards,
XY
