Forum Discussion
EEren
Occasional Contributor
Occasional ContributorA PLL problem.
I created a new project for MAX10 10M50SAE144I7G and copied a PLL and ADC modules in it. component pll is
port
(
inclk0 : in std_logic := '0';
c0 : out std_logic;
c1 : out std_logic;
c2 ...
sstrell
Super Contributor
Super ContributorSo the tool thinks a clock is needed somewhere else and is implementing an additional PLL for some reason. I think you'll have to check the timing analyzer to see all the clocks in your design to try to figure it out. Generate a clocks report to see all the domains. This might help you narrow down what is going on.
