Forum Discussion
EEren
Occasional Contributor
Occasional ContributorA PLL problem.
I created a new project for MAX10 10M50SAE144I7G and copied a PLL and ADC modules in it. component pll is
port
(
inclk0 : in std_logic := '0';
c0 : out std_logic;
c1 : out std_logic;
c2 ...
sstrell
Super Contributor
Super ContributorLike I said, it can't come from c3. You have to edit the PLL parameters and have the clock you want to use for the ADC to come from the c0 output of the PLL. So the c0 output should be 10 MHz and move the 120 MHz clock to c3.
EErenOK. I see. So I redesigned the PLL in Q-SYS. And now it's
U_SYS_PLL : pll port map ( inclk0 => OBE_CLK, c0 => s_pll_clk_10M, c1 => s_pll_clk_100M, c2 => s_pll_clk_30M, c3 => s_pll_clk_120M );But I get the same error.
