Forum Discussion
EEren
Occasional Contributor
Occasional ContributorA PLL problem.
I created a new project for MAX10 10M50SAE144I7G and copied a PLL and ADC modules in it. component pll is
port
(
inclk0 : in std_logic := '0';
c0 : out std_logic;
c1 : out std_logic;
c2 ...
sstrell
Super Contributor
Super ContributorThe PLL output driving the ADC must be c0 of PLL1 or PLL3 of the device. The no fit may be because you are not doing this. Switch the PLL outputs around to drive the ADC with c0 and see if that fixes the problem.
EErenIsn't it the same signal? Any way I've chaged it
SYS_ADC_SCAN : process(s_pll_clk_120M) --c0 from PLL variable chan : integer range 0 to 9 := 0; begin if rising_edge(s_pll_clk_120M) then ----------------------------------------and the ADC module gets 10 Mhz clock as it should
U_SYS_ADC : adc_qsys port map ( clk_clk => s_pll_clk_10M, --c3 from PLL reset_reset_n => '1',The problem still remains.
