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EEren's avatar
EEren
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

A PLL problem.

I created a new project for MAX10 10M50SAE144I7G and copied a PLL and ADC modules in it. component pll is port ( inclk0 : in std_logic := '0'; c0 : out std_logic; c1 : out std_logic; c2 ...
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sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

Where is glob_clock coming from?

EEren's avatar
EEren
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

It's coming from PLL

U_SYS_PLL : pll port map

(inclk0 => OBE_CLK,

c0 => s_pll_clk_120M,

c1 => s_pll_clk_100M,

c2 => s_pll_clk_30M,

c3 => s_pll_clk_10M );

glob_clock <= s_pll_clk_120M;