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Altera_Forum's avatar
Altera_Forum
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16 years ago

8b10b clock recovery?

Would it be possible to use an Altera FPGA (Arria II GX or Cyclone IV GX) to snoop on a 2.5 Gbps PCI Express link (via the PIPE interface), recover the clock and send out the recovered clock to one o...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Just to tie up all loose ends:

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Second best case jitter is to recover the clock and use it to trigger the scope viewing non-reclocked data.

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How did you recover the clock? I have found no circuit that actually outputs the clock from a 2.5 gbps 8b/10b diff signal. If the solution is fairly simple i could build this circuitry into the 'SMA board' and get better overall result.

Thanks.