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Honored Contributor
Honored Contributor8b10b clock recovery?
Would it be possible to use an Altera FPGA (Arria II GX or Cyclone IV GX) to snoop on a 2.5 Gbps PCI Express link (via the PIPE interface), recover the clock and send out the recovered clock to one o...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Basically your best case jitter is if you reclock the data and use the recovered clock to trigger the scope viewing the reclocked data. --- Quote End --- This is not a good option for me because i would no longer look at the actual data on the 2nd downstream PCIe connector. --- Quote Start --- Second best case jitter is to recover the clock and use it to trigger the scope viewing non-reclocked data. --- Quote End --- How did you recover the clock? I have found no circuit that actually outputs the clock from a 2.5 gbps 8b/10b diff signal. If the solution is fairly simple i could build this circuitry into the 'SMA board' and get better overall result. --- Quote Start --- I tested about 8 different methods. Using the complementary data signal to trigger the scope came in 6th. However, the test case was for pathological SDI data and your 8b/10b will perform better. Also, all you care about is rise/fall times and amplitude. You'll be fine. Jake --- Quote End --- This may be good enough if i can't figure out how to do the clock recovery. Thanks.
