8 MHz clock from 100 MHz

Like others have said the PLL isn't a licensed IP, all FPGAs have them and it's what I would think of as a basic feature (like on-chip RAM blocks for example). I would use the PLL wizard flow and not attempt to instantiate it manually in your RTL, it'll have a lot of parameters so using the wizard will save you a lot of typing and reading up on the IP. When you use the wizard you tell it your input clock is 50MHz and then you state you want an output clock of 8MHz and it will create an 8MHz clock (or as close as possible frequency). One thing to keep in mind is that it takes a PLL a while to "lock" so you should hold the logic it's connected to in reset until the locked signal from the PLL goes high. The locked signal is an optional signal so while you are in the wizard you'll see a checkbox to include it. When the PLL comes out of reset and is not locked yet you will see the output clock jitter which can cause stability issues in your own hardware so holding your hardware in reset waiting for the PLL to lock is a safe way to avoid this issue.

Once you are done with the wizard it'll generate some files for you that set the PLL up. You can use one of the wrapper files in your own RTL to instantiate it. If you have to adjust the PLL to change the frequency or maybe have it drive more clocks then you can reopen the wizard on the same PLL you previously generated.