8 MHz clock from 100 MHz

@sstrel

I am using a 50MHz clock for sampling in SignalTap II. Not much familiar with the PLL and also because of licensing issue of IP cores thought to skip it, but looks like that is the most feasible option. Thanks

@BadOmen

Yes you are right I mistakenly shared a different version of the code where the triggering limits for SCLK are different. Correct version is shared below with changes emboldened.

always @ (clk)
begin
	if (clk_counter < 5'b01011)
	begin
		clk_counter	<=	clk_counter + 5'b00001;
	end
	else if (clk_counter == 5'b01011)
	begin
		SCLK	<=	1'b1;
		clk_counter	<=	clk_counter + 5'b00001;
	end
	else if ((clk_counter > 5'b01011) && (clk_counter < 5'b11001))
	begin
		clk_counter	<=	clk_counter + 5'b00001;
	end
	else if (clk_counter == 5'b11001)
	begin
		SCLK	<= 1'b0;
		clk_counter	<=	5'b00000;
	end
end

Thank you for the reply. Actually this always block is triggered on both the edges of 100MHz clock. Since the 100MHz clock was needed to be scaled down by a factor of 12.5 and triggering on single edge would not have resulted in exactly 8MHz output clock. So what I did is that I compromised on 50% duty cycle of the clock by triggering the counter on both the edges and counted 12 edges for SCLK 's low logic and 13 edges for SCLK 's high logic to count 25 half-periods (or 12.5 full-periods) of 100MHz clock. Had the scaling factor been a positive integer I would definitely used a modulo counter.

https://www.alteraforum.com/forum/attachment.php?attachmentid=15843

I will try to make use of PLL but would still appreciate if someone can help me in diagnosing the reason of this unusual behavior of the 8MHz clock in Logic Analyzer.