8 MHz clock from 100 MHz

Did you attach the right code? It looks like SCLK is driven 0 when clk_counter is 0 and SCLK is driven to 1 when clk_counter is 13, then the clk_counter gets set back to 0 it reaches 25. So 26 100Mhz clock ticks doesn't result in a 125ns SCLK period.

By the way a clock divider is easier to understand if you just use a free running modulo counter and drive your output clock based on that counter being above or below a threshold. So if I was attempting to generate a clock close to 8MHz from a 100MHz source (you can't achieve exactly 8MHz by the way) I would have a 100MHz counter that cycles after it hits 12 then for count values below 7 drive sclk to 0, and above 7 drive sclk to 1 (assign sclk = (clk_counter < 5'h7)? 1'b0 : 1'b1). To minimize jitter I would also pipeline that sclk before driving any logic or pins with it.

Keep in mind that logic generated clocks will jitter more than a PLL output will. PLLs will be able to achieve the 8MHz frequency unlike a clock divider as well.