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I need all channels phase locked as precise as possible, saying channel difference/skew should be kept within several pico-seconds
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This a very difficult requirement. In the end at the output of each receiver has a 6.4 ns clock. Even if you carefully align all incoming streams,e.g. by feeding them from another FPGA using the same reference clock, you still risk having one clock of difference between the RX outputs.
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I think the problem is due to that each channel utilize its own PLL and there's no automatic calibration module or phase lock among these PLLs
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Each receiver locks to the incoming stream and needs to be self-supporting and thus to have its own PLL.
Honored Contributor
