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Thanks, Anand. Sorry for the confusion. My real question is about the output frequency of the PLL. Can it go up to 5.775 GHz, and can it be pumped out of the chip on a differential output like LVDS?
Regards,
Glenn
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The document referenced indicates the maximum PLL Fout is 550MHz for internal clock tree, and 667MHz for external clock pin (table 30 pp.40-41).
Where are you getting the 5.775GHz value from? I don't see that referenced anywhere.
I'm guessing it could be the PLL internal VCO maximum frequency, but there is no direct access to that node. It goes thru the PLL output divider first, which divides it down to the 550-667MHz range.
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