Honored ContributorHi,
How can I calculate the memory-bandwidth offered by a 4GB on-board SO-DIMM when I interface it with a Stratix EP3SL150 on a DE3 Board? Is this organized in 4 banks of 1GB? Can 1 controller access these banks, or would I need four controllers to maximize bandwidth? Thanks, ~FPGAKitty~
Honored ContributorThe available bandwidth from a DDR interface is determined by three things
Honored ContributorThanks Cajun-Rat!
One more question - how do we know the bit-width is 64 bit? [I risk sounding stupid] Is this FPGA-dependent? Thanks, ~FPGAKitty~Honored ContributorBy 'bit width' I mean the number of DQ pins on the SO-DIMM module. All SODIMMs have either 64 or 72 DQ pins. The 72 pin wide modules are generally used with ECC.
The only way to change this would be if you had a different Dev. Board, which might only have a single DDR2 chip and (say) 16 DQ pins. (DM and DQS/DQS# pins don't count as 'DQ pins')Honored ContributorHi,
I am using a CycloneIII and I would like to use a 4B SODIMM (MT16HTS51264H). When I create the HDDDR2 controller in SOPC Builder I get the following error: Error: cpu_0: Memory map cannot fit within the addressable memory space of the Nios II Data Master which is restricted to 31 address bits How do I implement a SODIMM controller properly. do you have any idea what is going wrong? Thank you, BriannaHonored ContributorAs the error message suggests, the NIOS processor can only address 2GB (31-bit address bus).
Honored ContributorThank you for the reply. When I change the DDR2 controller to interface w/ a 2GB sodimm I still get the same error. When I bring it down to 1GB then I'm alright. Does this mean I can only use a 1GB sodimm? I thought I saw other posts where people have successfully interfaced w/ at least 2GB.
