4-8 Channel ADC for Altera DE2-115 using Simultaneous Sampling

I have used the LTC1407A-1 from Linear Tech and interfaced it to Cyclone III and Cyclone IV many times on various boards I've designed over the years. They also make a LTC1407A, which is a unipolar part, while the LTC1407A-1 is a bipolar type part.

You just need SCLK, CONV, and SDO for each ADC. Each ADC Simultaneously samples two channels at 1.5 MSPS.

This is an excellent part, I have had good experience with it.

I'd be happy to help you with the VHDL driver.:)

James

Thanks a lot for the valuable information James. This looks to be a good part, but it still is 14-bits.

I have valuable data coming in from an accelerometer. So this data needs to be sampled to at least a 16-bit resolution.

So for a 16-bit, I tried to look this one up:

I tried to look up LTC1865 . Considering the sampling rate that I require, which is definitely less than 250khz, I guess this can be better than LTC1470.

I have looked up these too,

TI has the ADS8556 , which is good

Analog Devices has AD7606-6

But I havent worked with the Verilog/VHDL before much, just simple gate/logic/mux designing and am completely new to the NIOSII, so I do not know how I am going to interface this to the FPGA. I definitely know the SPI and I2C buses, but then, what about the driver for these ADCs and their initialization?

I appreciate your consideration in helping me out for the VHDL driver, which I must say will be extremely valuable to me, since I am a complete beginner at everything.

Wont the specific ADCs be required to be initialized using their specific firmware from the Manufacturer?

Also, I will have to design a board myself for interfacing this as a peripheral through the GP I/O lines on the DE2-115 board, right? Because this just comes in as a chip and I will have to put it on a GP board and come up with the Pull Ups and the Noise Cancelling Caps etc?

Excuse me for being to naive and asking stupid questions, but I am a complete beginner and have been assigned this task, which although doesn't have a deadline, needs to be completed at a satisfactory pace, since this is applied research for professor that I work for, and he hasn't worked on FPGAs ever before.

Hope you can help me more. Thanks a lot again!! :)

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I have valuable data coming in from an accelerometer. So this data needs to be sampled to at least a 16-bit resolution.

Considering the sampling rate that I require, which is definitely less than 250khz, I guess this can be better than LTC1470.

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Ok, so you have two important pieces of information here; you require 16-bits of dynamic range over a bandwidth of less than 125kHz (Nyquist bandwidth for sampling at 250kHz).

If the signal-to-noise (SNR) of the signal you are sampling is dominated by quantization noise, then you can oversample the signal, then digitally filter and decimate the signal. For every oversampling factor of 4, you gain about 1-bit in SNR, so to achieve 2-bits of SNR you need to oversample by 16x, i.e., 16 x 250kHz = 4MHz.

Don't the Terasic ADC boards operate at close to 100MHz?

I think you should try to look for an existing ADC board that can meet your requirements before trying to attempt to build your own.

For example, what does the signal you want actually look like? Go and use an oscilloscope or an ADC board and capture a few MB of data, then Fourier transform that data to look at its spectral response. How much dynamic range do you really have, is it 16-bits?

Cheers,

Dave

In general, to interface the ADC to Nios, you would need to write a driver for the ADC and then make the data available on the Nios bus. I tend not to use Nios much, as I write at the microarchitecture and finite state machine level. But you will need to study the datasheet of whatever ADC you pick, and then create an appropriate interface. This mean adhering to the setup and hold times admonished in the data sheet, whether it be from TI, ADI, or Linear Tech, etc. For a serial ADC interface, the VHDL (or System Verilog) will typically have counters, shift registers, and a state machine.

What I recommend you to do is to pick an ADC, write the driver, and write the outputs of the ADC to a simple PWM DAC. Then use Signal Tap to scope the output of your ADC driver, using various analog inputs, to verify the driver is working correctly. This would be academic after performing the digital design with a proper testbench.

Best, James

@Dave:

Thanks a lot. Yes, Terasic boards operate at very fast speeds. I am not trying to construct my own board for the time being. My professor too told me to look into existing boards and buy one out.

I will test the signal that you are talking to me about and check its spectral response and see if I actually need a range of 16 bits. If not necessary, then I can definitely go for ADCs which are more accurate or I can go by your idea of oversampling the signal for a better SNR.

Thank you Sir again for your valuable information.

@James:

I havent used either much, this is after 2 years that I am even getting back to Verilog programming. I appreciate all your help and advice.

I will however be selecting the correct ADC and will soon begin work with it and keep in mind your advice about the the testing and design.

Also, I might ask really lame and stupid questions or ask for help from time to time. Hope you dont mind helping me out.

Thanks a ton Sir!

Yash

I don't think that you'll find a HSMC daughter card according to your specifications. The said Terasic ADDA card, besides having only two channels also has transformer coupled in- and outputs and isn't suited for the intended frequency range without modifications.

TI offers a HSMC interface for their fast sampling ADC Evalboards. You can check if any of the available TI Evalboards is suited.

Following your application requirements, I would primarly think of the family of parallel sampling SAR ADCs with parallel interface, e.g. offered by TI. But I'm not aware of ready-made HSMC daughter cards using these ADCs.

@FVM:

Sir, thanks for the valuable information. I dont require the HSMC interface because I will not be using such high speeds for my DAQ and sampling. A simple SPI interface will be sufficient for the application that we are planning to use in our research.

That is the reason why I have been trying to look at the ADCs which I have mentioned above. Also, SPI interface drivers can be written/ the available ones I think so can be modified to suit my application.

If you have any more valuable information to add, please do. Thanks again sir.

PS: A quick question, is it possible to interface an Ethernet port to the DE-0 Nano board? If yes, how can it be done?

Yash

TI ADS8568 can achieve 400 kS/s over 8 parallel channels with a quad SPI interface. http://www.ti.com/product/ads8568

You need to interface an external PHY to implement an ethernet interface, I think, it's more convenient to use a DevKit with built-in PHY.

@James:

Can you suggest a good reference material for learning and implementing System Verilog For Embedded and Verification applications? Something which progressively increases in the difficulty level and can make a apply my hardware knowledge well.

Thanks a lot again for all the help until now. Will definitely ask for more!

Yash