New Contributor
Regular ContributorHello,
The MAX10 datasheet recommends a VCCIO voltage of 2.375 V < VCCIO < 2.625 V, but as the chip is single-supply, I would love to have a single 3V3 digital supply, as the board is very space constrained
The Vccio range for LVDS I/O Standard is from 2.375V to 2.625V. I will not recommend you to set it as 3.3V in this case as it can cause a permanent damage to your device.
Can I use a 3,3V VCCIO in Bank 3, when using true LVDS Rx/Tx ?
Yes but do not mix up more than one IO standard in a single I/O bank. True LVDS is supported only in Bank 3 for Max10 devices.
Could the emulated driver do it (in the other banks) ?
No
Are the LVDS receivers self-biaised (do I need to "make" the common mode voltage on the receiver end) ?
No, LVDS receivers in Altera® devices do not have on-chip dc-biasing resistors. If you are AC-coupling between an LVDS transmitter and an LVDS receiver in an Altera device, use an external DC-biasing network at the receiver end to achieve the required common mode input voltage (VICM).
I hope this answer help in your FPGA design.
Thank you and stay safe!
New ContributorThank you for your answers, I have a few more if you don't mind :
Is there a differential standard that I could use with 3,3V VCCIO ? Would I get a better data rate using Bank 3 IOs ?
I saw that the 10M08E144 Eval board powers its IOs with 3,3V, and uses its IOs in differential mode (100 ohms terminated). What is the "protocol" used ?
Regular ContributorHello,
There is no differential standard with that can use with 3.3 V VCCIO in Max 10. You can refer to Max 10 I/O Standard table from this link on table 4 page 9
Thank you.
