Honored Contributor
Honored ContributorAn answer!!! (I'm not crazy ... it is a Cyclone III (EP3C40) design error :eek: ).
Altera Support has confirmed, through their own independant testing, that these 3 pins on ALL EP3C40 devices have a current limit issue when running a boundary scan test on an unconfigured device! do not use af18, ah18, or ac11 on the ep3c40. Just don't use them. If you are going into a high enough impedance, they'll actually work just fine, but to be safe, I'd just leave them as No-Connects on your design. Again, if you use these three pins, you will have a current limit issue in boundary scan testing of unconfigured devices. So that means DO NOT use these pins with DDR termination (~50 ohms), or other fairly low resistance applications. And according to my testing, I would actually not go lower than 1 kOhm. If its too late for you, the work around is to create a boundary scan test for post-configuration. In order to get the same amount of coverage though, you will have to create a test image that has all pins (that aren't reserved) as bi-directional I/O. Then you'll have to create a custom BSDL file based on the .pin file for the test image. And you'll have to create a test step with a .jam file to load the FPGA before performing the boundary scan test. Not pretty, but that's what you'll have to do if its too late to respin your FPGA I/O and copper ( ... as is the case with my team's project). I have pasted below the response from Altera I got today on the matter ... There has been an update to your Service Request, 10711323. Please go to http://www.altera.com/mysupport (http://www.altera.com/mysupport) to view the update. The following " To Customer " note was posted: " Hi Jonathan, Sorry for the late response. We are currently testing on our device, and we observed that the output HIGH signal for these three pins are ~1.3V and output LOW signal are ~1.1V which are matched with your observation. While for other I/O pins, the HIGH signal is 1.9V and LOW signal is 0.5V. May I know what are the measurement for the other I/O pins from your side? We have run the IBIS simulation with the maximum (16mA) and minimum (4mA) current strength. The HIGH signal for 16mA is ~2.3V and LOW signal is <0.5V. The HIGH signal for 4mA is ~1.8V and LOW signal is ~0.7V. It seems like the current strength for these three pins are lower than 4mA. We are still seeking for the reason behind. Meanwhile, could you please run the boundary scan test in post-configuration mode or reassign to other pins as a solution? I will update you once we have any update on the progress. Thanks & regards, <name removed>
