2's complement consideration

I personally would always recommend the numeric_std package, as it defines all the operators needed and you can write much more clearly what you intend things to mean. Plus you can do signed and unsigned math in the same file that you cant with std_logic_vectors.

All integers are usually 2's compliment already. Unsigned or signed are already 2's compliment. unsigned numbers are just signed numbers with an implied '0' infront of them. are you actually talking about normalisation?

eg. taking a value in the range 0 to 255 and getting into the range -128 to 127 (normalising around 128)? for this you would subtract half of the range from the result (128), as you already suggested. This would be quite simple in VHDL using the IEEE packages.

Assuming you have a std_logic_vector input thats really an unsigned number:

signal normalised : signed(filter_op'high+1 downto 0);

variable temp : signed(filter_op'high+1 downto 0);

temp := signed('0' & filter_op); --make it a +ve signed number. Only need a variable as its a simple type conversion.
normalised <= temp - (2** (filter_op'length-1) );  --normalise it around 0