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Altera_Forum's avatar
Altera_Forum
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15 years ago

24bit counter by 400 MHz

Hi all,

i am working with Cyclone III Starter Kit, the max frequency is 400 MHz. I would like to use this high frequency to achieve a 2.5ns resolution.

with the megafunction i can easy make the 24 bit counter, however it works max at 325MHz. otherwise I recived critical Warning: Timing requirments not met.

it's clear, the more bit the more Propagation delay. however, is it possible, a 24 bit Counter work at 400 MHz?

I would not like to develope a TDC with the FPGA, it seems to be too complicated

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    The Max frequency specified in the documentation is only ever going to be a theoretical ideal maximum. You would struggle to actually achieve this. As you can see, the fmax it is reporting is 325Mhz, which is still pretty fast.

    Why do you need such a fast counter?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi Tricky,

    thanks for your reply,

    I need the fast counter to measure the time. we used a TDC card before, which has a 20ps resolution. to make it easy, I hope that I can do it with a simple counter. 2.5 ns Resolution is also ok.

    a 16 bit counter can work without problem at 400 MHz.

    the question is, if man can do something to optimize, so that a 24 bit counter also works at 400 MHz
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    If you want 24 bit counter running at 400MHz that is one issue, but if you just want 2.5ns time resolution then a single register running at 400 MHz may be do the job without counting. You send a changing input and check at the output of the register or Xor the input and output of that register resulting in a 2.5ns pulse.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Depending on your exact application, you might also use two counters at 200MHz, one with inverted clock, the other without. Then you can add the values of both counters. (You should ensure that the tsu/th from the pin to the counters is about the same for both counters. If the enable-input is directly a device-pin, you should add some synchronizer-stages, regardless if you use one or two counters.)

    If you combine this method with the cascaded counter someone mentioned, you can achieve even higher resolutions if required.

    Regards,

    Thomas
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    Depending on your exact application, you might also use two counters at 200MHz, one with inverted clock, the other without. Then you can add the values of both counters. (You should ensure that the tsu/th from the pin to the counters is about the same for both counters. If the enable-input is directly a device-pin, you should add some synchronizer-stages, regardless if you use one or two counters.)

    --- Quote End ---

    Not quite: because both counters will be enabled by the same input pin you have a redundancy: at any moment in time the count in the two counters will only differ by maximum 1. One counter will have count 'n', the other will then either be 1 less, equal or 1 more. The sum will then either be 2n , 2n - 1 , or 2n + 1. The second case 2n + 1 equals 2(n +1) - 1. So you can obtain the same effect with a single counter and a smaller prescaler (of 1 bit size) circuit, which could be operated with both edges of the clock or double the frequency. You would need a equivalent circuit to drive the proposed 2-counter solution as well.

    Regards,

    someone :)