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Altera_Forum
Honored Contributor
9 years agoHi thanks!
As for question1, I did some research on PS2 keyboard as input for FPGA and found an answer. Seems like keyboards use a Make and Break Code whose number of bits depends on the button pressed (Arrow keys has more). Anyway, question 1 is solved. Thanks for suggesting PS2 keyboards. Sorry for the noob question, stuffs like these are the things that anyone can figure out on their own. I should have done more research before asking. As for question2, I saw some youtube videos using VHDL as the HDL for Altera Cyclone II DE1 Board and it works fine. I couldn't find any reason why it would not be supported because VHDL is one of the major HDL What's the standard I/O constraints? Can you give an example? Thanks in advance (+rep)