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Altera_Forum
Honored Contributor
Honored Contributor2 clock domains or NOT?
Hello, Just need a suggestion from experiensed engineers how the following situation can be considered. I have a PLL which generates 20 Mhz from 24Mhz. Next I feed it outside an FPGA. N...
Altera_ForumHonored Contributor
Honored ContributorThe 20Mhz and 25MHz clock domains should be treated as two separate clock domains. However, in this particular case there is a relationship between the two.
Problems? Problems between clock domains normally only occur when you are trying to pass logic between the two domains. (A deeper discussion might get into physical problems with multiple domains (routing resources, jitter, noise, etc.). If you are not crossing clock domains, then there is no issue. If you are crossing domains then you need to use proper domain crossing techniques (dual-clock FIFO(s), RAM, synchronization circuits, etc.). Jake
