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first, does the clk input in the packetbitconverter block synchronizes the Q1...Q4 outputs ? (does the Q1...Q4 outputs changes on each edge of clk ?)if yes, then fulldataclk could be connected to clk.
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yes, the output will be available at posedge of the clk.
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fifoclk is the clock connected to the wrclk of the fifo, choose for its frequency, any value that's at least 4 times bigger than fulldataclk (so as to be able to stock all the four values Q1..Q4 in the fifo, before they change)
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right now, i used the same clock as clk for fifoclk(wrclk). the output at Q1 to Q4 will not change until Q4 has been transferred to fifo. is that possible to do so? i will need to de-assert "en" signal to clear the Q outputs.
thanks
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