Honored Contributor
Honored Contributori suggest to add an intermediate module between the two blocks, see the picture in attachment, you must feed that block with two clock signals : the fifoclock input determines the writing speed to the fifo, and the fulldataclock input is the clock that synchronizes data on Q1, Q2, Q3 and Q4. I assumed that on the rising edge of fulldataclock, data on Q1,...,Q4 changes. In order to do the task correctly, the frequency of fifoclock must be at least 4 times bigger than the frequency of fulldataclock.
the material description of the block is in the file inter4to1.v in attachment note : i didn't test the verilog code yet, but logically it must work
