10GE Ethernet Solution in Stratix 10 Device

Hi Linu,

Stratix 10 devices suggested for E-tile hard IP:

1. Stratix 10 TX Transceiver Signal Integrity Development Kit-1ST280EY2F55E2VGSI
2. Stratix 10 TX Transceiver Signal Integrity Development Kit-1ST280EY2F55E2VG

We suggest above Stratix 10 devices for E-tile Hard IP because it provide the design example for the above device.

For further details information about E-tile Hard IP Intel Stratix 10, you may refer link below, https://www.intel.com/content/www/us/en/docs/programmable/683578/22-4/design-example-31391.html

Best regards,

Zi Ying

Hi Zi Ying,

Thank you for the reply.

The Stratix device in the development board is the highest device in Stratix 10 device.

As per the resource utilization of Etile Ethernet Hard IP , can you suggest a lower device in Stratix 10 that can verify the IP.

Since we are planning to do a custom board , we are looking for an optimal FPGA for the Ethernet design.

Also do we need to purchase the license for using ETile Ethernet Hard IP. In the datasheet its mentioned that the Hard IP is available with the IP Catalogue in Quartus Software . Can we directly instantiate in our design and download in Hardware. Or do we need to purchase a license to use the ETile Ethernet Hard IP.

Regards

Linu

Hi Linu,

Q1. As per the resource utilization of Etile Ethernet Hard IP , can you suggest a lower device in Stratix 10 that can verify the IP. Since we are planning to do a custom board , we are looking for an optimal FPGA for the Ethernet design.

Ans: As per my understanding according your question, you want to implement the E-tile Hard IP on Stratix 10 devices. I would suggest you to use either Stratix 10 TX or Stratix 10 MX devices to implement the E-tile Hard IP on Stratix 10 board.

Q2. Also do we need to purchase the license for using ETile Ethernet Hard IP.

Ans: When the evaluation time expires for any licensed Intel FPGA IP in the design, the

design stops functioning. All IP cores that use the Intel FPGA IP Evaluation Mode time

out simultaneously when any IP core in the design times out. When the evaluation

time expires, you must reprogram the FPGA device before continuing hardware

verification. To extend use of the IP core for production, purchase a full production

license for the IP core.

You must purchase the license and generate a full production license key before you

can generate an unrestricted device programming file. During Intel FPGA IP Evaluation

Mode, the Compiler only generates a time-limited device programming file (<project

name>_time_limited.sof) that expires at the time limit.

Best regards,

Zi Ying

Hi Linu,

Currently we can't provide the example design with public due to the confidential of company.

Regarding the license of E-tile Ethernet Hard IP, you are required to buy the IP license if you wish to use it. For your information, the E-tile Hard IP is not included in the Quartus software tool and it is licensed IP. In shortly, you are required to buy the license separately.

Best regards,

Zi Ying

Hi Linu,

The IP cannot be used in any Intel FPGA device and it need depends on what IP used. Some IP only support in certain devices.

The E-tile Hard IP only can support in Intel Stratix 10 and Intel Agilex devices.

For further details about the E-tile Hard IP for ethernet Intel FPGA IP device family support, you may refer Section 2.3.1, pg 17, https://www.intel.com/content/www/us/en/docs/programmable/683468/22-3/intel-fpga-ip-device-family-support.html

For further information about licensing, you may refer to link below, https://www.intel.com/content/www/us/en/docs/programmable/683102/21-3/introduction-to-cores.html

Best regards,

Zi Ying

Hi Linu,

Since I have addressed your question and no hear any feedback from you, I am now close the case. If you have any question after the case closed, please do feel free to submit another issue.

Best regards,

Zi Ying