10AS066H2F34I1HG FIT and MTBF value

Hi,

You can find information in below link.

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/rr/rr.pdf

https://www.altera.com/support/support-resources/knowledge-base/solutions/rd06132000_3184.html

https://www.altera.com/support/support-resources/knowledge-base/solutions/rd12222008_705.html

https://www.altera.com/support/support-resources/knowledge-base/solutions/rd04072012_59.html

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

Hi,

You can use PN:MAX1619.

Refer the arria10 development kit schematic for interfacing details and handbook page no:310 & 311 for connection guideline.

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/arria-10/a10_handbook.pdf

https://www.altera.com/content/dam/altera-www/global/en_us/support/boards-kits/arria10/soc/production_files/a10_soc_devkit_03_31_2016.pdf

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

Hi,

Refer

https://www.altera.com/en_us/pdfs/literature/sg/product-catalog.pdf

https://www.altera.com/documentation/sam1403480274650.html#sam1403480019500

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

Hi sir,

Thanks for sharing, I am aware of those documents you have shared. It consists of the following power option.

S : Standard

L : Low

M : VCC PowerManager

But customer has provided us with the part number 10AS066H2F34I1HG. Can i know what does that H refer to?

Hi,

H refers to High performance power.

For more details on this you can check the links in pervious post.

https://www.alteraforum.com/forum/attachment.php?attachmentid=14710

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

Hi,

We are using 10AS066H2F34I1HG. What is the allowed (minimum and maximum) ppm tolerance for input clock for FPGA DDR4 Clock and HPS DDR4 clock?

Regards,

Bhavishya AJ

Hi,

There is no ppm spec for DDR4 refclk. Both FPGA and HPS DDR4 refclk will be connected to IOPLL input clock pin.

For IOPLL input clock spec, we only have jitter spec as shown in attached A10 datasheet.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

Hi,

Thanks for your reply.

Where can I get the following documents

1)IBIS model and associated documents

2)insertion and jitter loss documents for 10AS066H2F34I1HG?

Regards,

Bhavishya AJ