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Honored Contributor
Honored Contributor100KHz 16bit PWM generation -- PLL manipulation?
I would like to replace my TI Picccolo with an FPGA. The one major thing that the Piccolo has is the ability to generate a PWM signal with a resolution of 150 ps (yes, pico seconds), thus allo...
Altera_ForumHonored Contributor
Honored ContributorTo deal with "PLL dynamical phase shift ... only by single phase increment at PLL scanclk" It would make a lot more sense to deal with the first 10 Most Significant bits using the 100Mhz Clock (holding the Set in place) then use the 6 least significant bits to adjust the PLL.....thus I could go from 90% to 10% in one cycle.
