100KHz 16bit PWM generation -- PLL manipulation?

Just to check my understanding-----

Fractional PWM modulator --

So for a simple case, int1=XXX, int2=int1+yyy (where yyy=1) every other cycle gives you one extra bit of resolution.... change the range of yyy to 4 give you 2 extra bits, etc....with an associated increase in the appearant 'ripple'

"PLL dynamical phase shift ... only by single phase increment at PLL scanclk" -- this seems like an odd limitation, based on how fast the VCO can change I guess? -- anyway, so at the 100Khz Cycle by Cycle PWM this would mean that the maximum step change per PWM cycle would be 1000 (100Mhz/100khz), thus requiring 66 PWM cycles (2^16/1000) or 660 us to get from the max duty to the minimum duty.