100KHz 16bit PWM generation -- PLL manipulation?

Fractional PWM modulator possibly isn't an unequivocal term. Fractional PLL or fractional clock divider in contrast is. The common idea is to achieve additional resolution by switching between two integer values in a defined pattern. An error accumulator makes the average value follow the ideal setpoint. If you can use fractional techniques without adding noticeable noise power within in the utilized signal spectrum depends on the available output filtering and partly on the algorithm to generate the modulation pattern. It can be e.g. a higher order sigma delta modulator.

Regarding PLL dynamical phase shift, you have to consider the restriction, that the PLL phase can be shifted only by single phase increment at PLL scanclk (100 MHz max.) speed. If dynamical phase shift is applied to multiple outputs of a PLL, the time budget has to be shared. The method seems to be fast enough to achieve a by-cycle setting for a 100 kHz PWM.