100KHz 16bit PWM generation -- PLL manipulation?

I would like to be able to update the duty cycle every cycle (aka. every 10us, probably computing the error one or 2 cycles behind). Basically a PID loop would be reading in the next destination voltage for calculating the 'error', and stuff that resutiling PWM Duty Cycle into a 1 or 2 deep fifo. The negative edge of the PLL output would load in the next value into the phase shifter. That value would encode the width of the positive pulse. The beginning of that pulse would come from a 100khz clock. The duration of the pulse would be determined by the PLL/phase shifter. The PWM duty cycle would be limited to between 10% and 90%, to ensure that I have calcuated the next positive pulse width.

If I can do this with a $30 Cyclone III then it will only need to handle 3 of these PWMs per chip. (I will need 27 PWMs total per box, but using several FPGAs should be fine.....the master controller will probably be a Stratix or 2 that will be feeding the Cyclone's next value.)

What is a "fractional PWM modulator", the great google did not find that term (other than your post!)