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Honored Contributor
Honored Contributor10 errors on my analog input signal (smart led) code pls help!
library IEEE; use IEEE.STD_LOGIC_1164.all; ENTITY sirisha IS port ( temp :in std_logic_vector(6 downto 0); CLK :in std_logic; enable :in std_logic; day , ...
Altera_ForumHonored Contributor
Honored ContributorYou have a lot of issues I am not good in VHDL but you need a begin after your architecture and before your concurrent statements also for else if it should be elsif. In your process blocks you name the process but you need a colon and word process before your brackets. Here is some info.
http://www.gmvhdl.com/process.htm http://www.vhdl.renerta.com/mobile/source/vhd00005.htm http://www.ics.uci.edu/~jmoorkan/vhdlref/ifs.html
