Forum Discussion
Altera_Forum
Honored Contributor
10 years agoYou have a lot of issues I am not good in VHDL but you need a begin after your architecture and before your concurrent statements also for else if it should be elsif. In your process blocks you name the process but you need a colon and word process before your brackets. Here is some info.
http://www.gmvhdl.com/process.htm http://www.vhdl.renerta.com/mobile/source/vhd00005.htm http://www.ics.uci.edu/~jmoorkan/vhdlref/ifs.html