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Altera_Forum's avatar
Altera_Forum
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16 years ago

10 Base ethernet Transmitter issues

Hey, I know that is not the most proper area to place this question but i think there are many who can give me a tip on this matter. When i have to design the circuit , i have to implement...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks for the reference FVM, i got some vital specifications about my needs.

But i have a question, i had been concitrated on the fpga4fun.com 10base ethernet project (http://www.fpga4fun.com/10base-t0.html) and i am asking: It will be any clock issue if I use this project (20Mhz) combined with a Phy Chip (25Mhz) ?

I am cornered on this matter and i dont know what to decide.

1.Follow the fpga4fun project without PHY and face collisions, or

2.Modify the source code and add a PHY chip to solve these problems.

Ref: http://www.fpga4fun.com/10base-t0.html (http://www.fpga4fun.com/10base-t0.html)

PS. I will only implement the Transmittion part ( Half Duplex)

Thank you for your time. :)

Friendly Giannis