New Contributor
Super ContributorWe do not receive any response from you to the previous question/reply/answer that I have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.
New ContributorHello,
I was able to use the MIF file.
However I used a VHDL model of the ROM, instead of the Verilog, as I could not get it working as mentioned.
The link you provided, is about converting MIF to HEX. And I was still able to use the MIF file.
So the problem is still there, when I use the Verilog model, but not when I switched to the VHDL model of ROM.
I have been using the ModelSim Altera version, which comes with Quartus 20.1 Lite edition.
Thank you,
Super ContributorCould you help to share a simplified design files with the issue duplicable so I could investigate further?
Please help to provide briefly the steps to reproduce the issue. It helps to duplicate the issue faster.
New ContributorHello,
I have attached the files. Please let me know of your findings.
(I have renamed the MIF file to TXT extention, as your website doesn't allow to attach it. So please change and save it with MIF extention, on your side.)
- Top file 'OnePortRom.v' - Test Bench 'OnePortRom_tb.v' - Rom model verilog 'RomMem.v' and 'RomMem_bb.v' - Rom model VHDL model 'RomMemVhdl.vhd' - MIF file 'RomInit.mif'
Thank you,
Jaspal
New ContributorHello,
Is there an update from your side about this issue?
Were you able to simulate and recreate the problem, on your end?
Thank you
New ContributorHello Intel Support,
It's been over a month now since I provided the files?
Do you have any update?
Super ContributorSorry for the delay in response. I forget to re-open the case thus it was closed, till a reply notification come in.
Try to run using the Nativelink feature in the Quartus Lite/Standard.
1. Create a Project with the OnePortRom.v and RomMemVhdl.vhd file
2. Follow the steps 6-8
3. Tools > Run Simulation Tool> RTL simulation
4. Modelsim will auto simulate the result for you.
Initially only clk_tb, out_tb and a signal waveform are shown. You will need to manually add the other signals that you are interest to check.
