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Altera_Forum
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8 years ago

1.8V HSTL Differential DDR output using ALTDDIO_OUT on Cyclone 10 LP

I need to drive multiple 1.8V HSTL differential pairs from a Cyclone 10 LP FPGA. The output is DDR, source synchronous. I am currently doing this with single-ended signals using the ALTDDIO_...
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Altera_Forum
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8 years ago

Thank you for your reply, FvM.

I originally tried to do as you suggest. The pin-planner does not give me the option of 1.8V Differential HSTL Class I on most I/O pins. Digging further in the "Cyclone 10 LP Core Fabric and General Purpose I/Os Handbook", pg 102 says:

the following differential i/o standards are supported only on clock input pins and

pll clock output pins:

— differential sstl-2 and differential sstl-18

— differential 1.8 v hstl, differential 1.5 v hstl, and differential 1.2 v hstl

So, I believe I cannot use the differential output standards on normal I/O pins. Or is there something I'm overlooking?

Ultimately, I'm needing 5 differential output pairs to drive a MIPI CSI-2 output. The Altera app note: "AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel Low-Cost FPGAs" recommends using the differential 1.8V HSTL outputs.

Maybe the closest I can come is using two single ended 1.8V HSTL outputs. What do you all think? Then my question is how to drive them both from a ALTDDIO_OUT megafunction?