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ymiler's avatar
ymiler
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3 years ago

Worst-case operating conditions

The timing analysis is performed to check for violation with the fastest speed grade "type" of FPGA defined in the project and with the slowest for the upper and lower temperature limit I would li...
sstrell's avatar
sstrell
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3 years ago

No. The operating conditions/timing models are specific to the device you are targeting. When you manually generate the timing netlist, you can select a different speed grade of the same device, but other than that, the models to use are baked into the timing analyzer.

ymiler's avatar
ymiler
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3 years ago

OK thanks