Forum Discussion
ymiler
Contributor
ContributorWorst-case operating conditions
The timing analysis is performed to check for violation with the fastest speed grade "type" of FPGA defined in the project and with the slowest for the upper and lower temperature limit
I would li...
sstrell
Super Contributor
Super ContributorNo. The operating conditions/timing models are specific to the device you are targeting. When you manually generate the timing netlist, you can select a different speed grade of the same device, but other than that, the models to use are baked into the timing analyzer.
- ymiler
OK thanks
