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ufuk's avatar
ufuk
Icon for New Contributor rankNew Contributor
1 year ago

Which values can I poll from credit register while doing CvP of Stratix 10?

Hello,

I have a board with Stratix 10 and OpenCL applications has been working properly. I want to use it as CvP. I programmed QSPI flash with periph.jic and trying to load core image(core.rbf) over CvP driver.

When I am trying to read extended configuration space, all data seems correct for CvP but "0x0" value is in the credit register (offset: 0xBC8). I can manage initial steps of CvP but when I am trying to send core.rbf data as 4K sizes to the device, it fails after two packets sent. Actually, it seems no reply for CvP data. I wait until credits are granted but the credit register has always zero value.

Example Workflow:

  1. Initial Polling: Start by reading the credit register to determine if any credits are available.

  2. Send Data: When you observe that credits are available (i.e., the register shows a non-zero value), send the corresponding amount of configuration data (e.g., 4 KB per credit).

  3. Continuous Polling: After sending data, continue polling the credit register to check for additional available credits before sending more data.

  4. Completion: Repeat the process until all configuration data has been sent.

1- Which value must be set in the credit register before starting CvP process?

2- Which values will be set while doing CvP process from start to end?

Thanks in advance.

Fpga Devkit

2 Replies

  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

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  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hello,


    I am sorry for late reply.


    For CvP (Configuration via Protocol) on Stratix 10, the credit register plays a critical role in managing the flow of data between the host and the FPGA during the configuration process.


    Initial Credit register value:

    Before CvP start, the credit register (offset 0xBC8) should contain a non-zero value once the FPGA is ready to receive configuration data. This value represents the number of 4 KB data blocks (credits) that the FPGA can handle at that moment.

    A value of 0x0 in the credit register indicates that the FPGA is not yet ready to accept data.


    please check below items :

    • Incorrect programming of the periph.jic file.
    • An issue with the CvP configuration process initialization.
    • A mismatch in the PCIe link settings or the CvP driver setup.


    Summary of Register behavior:

    Initial Polling-> Cdt Register value: Non-zero (number of available 4 KB credits)
    During Data Transfer-> Cdt Register value: Decreases as data is sent
    After Transfer
    -> Cdt register value : 0x0
    if all data has been sent



    regards,

    Farabi