What is the highest frequency of the h2f_axi_clk and h2f_lw_axi_clk clocks?

Hi,

May I know first which device you are referring to actually? Cyclone V SoC, Arria 10 SoC etc.

Hello!

I am sorry. I have forgotten to specify the device, it is Cyclone V SOC, part number is 5CSEBA4U19I7N.

Now I am using the following configuration:

1. AXI FPGA-to-HPS bridge clock (h2f_axi_clk) is 200MHz, the data width is 128 bits.

2. There are baremetal, Intes`s Hwlib and FreeRTOS.

The device is working properly. The maximum transfer rates (between CPU and FPGA on-chip memory) that I have achieved are:

When access through a range of virtual addresses with attribute ALT_MMU_ATTR_NC:

1. CPU write data to FPGA is ~1216 MByte/sec.

2. CPU read data from FPGA is ~450 MByte/sec.

When access through a range of virtual addresses with attribute ALT_MMU_ATTR_DEVICE:

1. CPU write data to FPGA is ~571 MByte/sec.

2. CPU read data from FPGA is ~406 MByte/sec.

Data sizes range is 32768 bytes.

These rates are enough for our application, but I would like to try to increase their without

using DMA, simply increasing the frequency of h2f_axi_clk.