What is the effect of nCE on passive serial configuration

Could you explain how you program FPGA #2, without programming FPGA #1?

As far as we know, this is not possible, but it is a requirement for us.

Our design looks like:

We plan to have a programming cycle like this for Device 1 in our diagram.

As far as we understand, both Device 1 and 2 in our diagram are connected as FPGA Device 2 in your picture.

That is: the device will see nCONFIG pulsed low, while its nCE is high.

So we have the following questions about device #2 in the passive serial programming for multiple FPGAs.

• Can you confirm that device #2 in your diagram is reset when nCONFIG goes low even though the device is disabled (nCE is high)?
• Can you confirm that device #2 in your diagram is not affected by any transitions on DATA0, DCLK while the device is disabled (nCE = high)?
• Can You confirm that once the set number of configuration bytes have been sent on DATA0, DCLK any bytes following that are ignored.
• Can you confirm that once nCE goes low on device #, incoming data is accepted immediatel(no delay)?
• What happens with the I/O pins if nCE goes high after configuration?

We see that this is how it is going to look like for a full configuration.

Best Regards

Ulf