What is the effect of nCE on passive serial configuration

We are not using active serial, we are using passive serial, where a CPU has the configuration data in its flash and configures the device using an SPI bus where we expect to use standard SPI drivers.

this means that we pulse config, wait for status and then do an SPI transfer. nCE is high until the SPI transfer starts.

We are using TWO FPGAs, and we want to program them independently from each other.

That is why the nCE pin is not grounded.

This means that we are not connecting nCE of the first FPGA to GND and we are not connecting the nCEO of the first FPGA to the nCE of the second FPGA. This is how you do it if you always want to configure both FPGAs at the same time.

The nCE pin of FPGA #1 is connected to a GPIO pin of the MCU.

The nCE pin of FPGA #1 is connected to another GPIO pin of the MCU.

This configuration is not described directly in your datasheets or application notes, but this is how the *SECOND* FPGA works when you do passive serial configuration for more than one FPGA.

So please reread my questions, and please try to answer the question.

Any answer that says that nCE should be tied low fails to understand the question.

The question is what happens in the FPGA if you pulse nCONFIG low while nCE is high?