using RAM memory on de1 board (Cyclone II)

hellol,

I have a question about reading and writing from the RAM memorys that are on-board of the DE1.

from what i have read: there are 3 types of memory installed:

8Myte SDRAM, 512 Kbytes Sram , 4Mbytes flash.

i want to use the ram memory (dont know who should i choose)

and found this code templtae in quartus:

--- Quote Start ---

-- Quartus II VHDL Template

-- Simple Dual-Port RAM with different read/write addresses but

-- single read/write clock

library ieee;

use ieee.std_logic_1164.all;

entity simple_dual_port_ram_single_clock is

generic

(

DATA_WIDTH : natural := 8;

ADDR_WIDTH : natural := 6

);

port

(

clk : in std_logic;

raddr : in natural range 0 to 2**ADDR_WIDTH - 1;

waddr : in natural range 0 to 2**ADDR_WIDTH - 1;

data : in std_logic_vector((DATA_WIDTH-1) downto 0);

we : in std_logic := '1';

q : out std_logic_vector((DATA_WIDTH -1) downto 0)

);

end simple_dual_port_ram_single_clock;

architecture rtl of simple_dual_port_ram_single_clock is

-- Build a 2-D array type for the RAM

subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);

type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;

-- Declare the RAM signal.

signal ram : memory_t;

begin

process(clk)

begin

if(rising_edge(clk)) then

if(we = '1') then

ram(waddr) <= data;

end if;

-- On a read during a write to the same address, the read will

-- return the OLD data at the address

q <= ram(raddr);

end if;

end process;

end rtl;

--- Quote End ---

now, i undestand that it does an 2-D array but there i things that i dont figure:

1. if the adress witdh is 8 and word size is 6 that makes a: (2^8 *6) = 512bit memory right?

2. how can i connect this entity for it to use the wanted memory?

3.what memory should i choose:SRAM or SDRAM (i need to work on dual mode)

thank alot

Pini Sberro