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Mahdi's avatar
Mahdi
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

Understanding address map in EMIF

Hi, I am trying to read/write from/to an external memory model during the simulation using EMIF. I have some questions regarding the address map in EMIF. Based on this configuration, what ...
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    4 years ago

    For the address ordering that you used:

    CS-CID-Row-Bank-Column-BG

    The CS is available only when there is multiple rank.

    The CID is for 3D stacked interface. No CID bit in this configuration.

    Row address width = 15.

    Column address width = 10.***

    Bank address width = 2.

    Bank group width = 2.

    ***(Lower 3 bits has been set to 0 because Avalon bus is 8x wider than EMIF bus in Quarter rate. Therefore it's removed when mapping to Avalon address)

    The ordering will be as below:

    Row[14..0] = amm_address[25..11]

    Bank[1..0] = amm_address[10..9]

    Column[9..3] = amm_address[8..2]

    BG[1..0] = amm_address[1..0]

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Mahdi,


Thank you for submitting your question in Intel Community.

I'm Adzim, application engineer will assist you in this thread.


In my opinion, you need to refer to memory datasheet for the truth table of the memory commands.


Cheers,

Adzim


Mahdi's avatar
Mahdi
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Hi Adzim,

Thanks for your reply. I am not using the actual memory system. I am using the memory IP core that is generated in EMIF design example, and I do not know its specifications.

- Mahdi