Two questions regarding the Avalon-MM DMA IP core

Hi,

This means that if I have 128 descriptors, the 128th descriptor might be completed before the 1st descriptor. May I ask if I can turn off this out-of-order completion feature?

--Your understanding is correct. This feature is for bandwidth efficiency. I'm afraid you can't turn it off since this feature is not transparent to the application layer. Two things you probably can do if you want completion in-order:

1. Read request not over 4KB. This doesn't guarantee especially when packet through multiple switches.

2. Not send next request until last completion is received.

Another way is to use Avalon-MM with your own DMA. Thus you have full control of the packet flow.

May I ask what the addressing range of BAR0 in this IP core is?

--You can find the BAR address and size In lspci info like below.

Region 0: Memory at 6020000000 (64-bit, prefetchable) [size=512]

Region 2: Memory at 6000000000 (64-bit, prefetchable) [size=512M]

Regards,

Rong