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New ContributorTripple speed ethernet IP
New ContributorHello,
Yes i have taken the same approach. I have made an example with using TSE IP . Please find PDF file of design example & share your view.
Thanks for your reply.
https://drive.google.com/file/d/15RMoVfk7B6L_ZW7DwtMOSw33JLrcrYS5/view?usp=sharing
- skbeh
Contributor
Your block diagram consists of TSE core, transceiver native phy, PLL, transceiver reset controller, msgdma, it looks fine and is similar to one of the example available at below link.
Arria 10 - Triple-Speed Ethernet and Native PHY design example:
https://www.intel.com/content/www/us/en/design-example/715131/arria-10-triple-speed-ethernet-and-native-phy-design-example.htmlDocumentation User Guide:
https://www.intel.com/content/dam/altera-www/global/en_US/uploads/e/e0/Arria_10_Triple_Speed_Ethernet_and_Native_PHY_Design_Example_User_Guide.pdf
