Hello, Currently, I passed all setup, hold, recovery and removal timing within the FPGA with constraint all paths and I/Os, but my I/O through GPIO portion did not passed the timing. Do you have any...
Don’t worry about this issue and I know how to interpret the LAB location now, but I don’t know why timing report didn’t change. As I know Synopsys timing report should change even some 10 pico second change. Could do some experiment in your side with any small testcase? I really feel wired for the timing report even I locked different location. Thank you in advance!
Oh the command is set_location_assignment is hard lock
HI YY,
I see. Thanks for your quick response. Currently I add new commands in qsf file as following as:
set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataL[2]"
set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataL[0]"
set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataH[3]"
set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataL[1]"
set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataL[6]"
set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataH[6]"
set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataH[2]"
set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataH[0]"
set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataL[3]"
set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataH[1]"
The timing report is still has [cid:cdf2b8ff-bd8b-41ee-9023-b788567e7ff3]
The floorplan placement which matches constrain as following as
[cid:74445102-84c9-44b8-a9af-dc4882e6e8be]
Before I put above constraints, the floorplan placement is as below routing with same report delay, but routing distance cross a lot of LABs comparing above and below placement, so I suspect timing report is wrong. As I did Synopsys ICC2 timing project back three years ago, these distances should have different timing report because net delay has a big difference. Since I/O pads fix the location, you can figure out rest of constrains to do experiments.
[cid:7fd1c7c8-fc24-4aac-9c3e-92c450438757]
I used 10AX027H4F34I3SG device.
Thank you so much!
-Fred
Occasional Contributor
