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Petkov_Alex's avatar
Petkov_Alex
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

Stratix V PCIe CvP not working

Hello! I have a board with Stratix V GT, PCIe HIP works good at Gen3 x8. I want to use it as CvP. So, i downloaded reference design, made chnages in assignment editor and compiled project. My setti...
  • Wincent_Altera's avatar
    Wincent_Altera
    3 years ago

    Hi,


    Thanks for the additional information and printscreen, Apologize for missing some important information.

    I do a deep check for Stratix V CvP gen2 procedure.


    Indeed Stratix V does support CvP at Gen2, due to a published errata, customers must order specific product variants with fixed silicon.

    Please see errata, PCIe Gen2 Link Training Error When Using Hard Reset Controller. As CvP must use the hard reset controller, then this errata applies.

    https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/es/es_stratixv.pdf#page=2


    The good news is that a fix part is available, your customer is reported as using:

    5SGSED8N2F45I2L

    But they must order parts with the full part number:

    5SGSED8N2F45I2LCV


    The *CV indicates fixed PCIe Gen2 silicon Hard Reset Controller.

    Without fixed silicon, only Gen1 is supported in Stratix V.


    Hope this clarified,

    Regards,

    Wincent_Intel


Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

*** repost due to typo at recent sent


Hi,


Thanks for the additional information and printscreen, Apologize for missing some important information.

I do a deep check for Stratix V CvP gen2 procedure.


Indeed Stratix V does support CvP at Gen2, due to a published errata, customers must order specific product variants with fixed silicon.

Please see errata, PCIe Gen2 Link Training Error When Using Hard Reset Controller. As CvP must use the hard reset controller, then this errata applies.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/es/es_stratixv.pdf#page=2


The good news is that a fix part is available, Please refer to KDB below

https://www.intel.com/content/www/us/en/secure/support/programmable/articles/000083884.html


The *CV indicates fixed PCIe Gen2 silicon Hard Reset Controller.

Without fixed silicon, only Gen1 is supported in Stratix V.


Hope this clarified,

Regards,

Wincent_Intel



Petkov_Alex's avatar
Petkov_Alex
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
For the first question thanks a lot for excellent explain!
For the second question, about pesrtn pin. Maybe i explained not good. I have board, where pin perstn from pcie is not, where expected for hard reset. So pin, where actually comes perstn is iodiff pin, and perstn pin expected for hard reset not connected anywhere (
If I disabled cvp and make assignment gor pin that comes to hard reset "weak pullup resistor", and program.sof file or jic files. My pcie works good.
But if i enable cvp, and split sof file to periph.jic and core.rbf files it seems that assignment with "weak pullup resistor" not used in periph.jic and putted by quartus to core.rbf file.
If i try to use my pin where developer of board putted nperst from pcie slot, fitter goes to error because hard ip expect other pin.
I hope I explained better this time.
Hope any help.