Forum Discussion
Occasional ContributorStratix V PCIe CvP not working
Hi,
Thanks for the additional information and printscreen, Apologize for missing some important information.
I do a deep check for Stratix V CvP gen2 procedure.
Indeed Stratix V does support CvP at Gen2, due to a published errata, customers must order specific product variants with fixed silicon.
Please see errata, PCIe Gen2 Link Training Error When Using Hard Reset Controller. As CvP must use the hard reset controller, then this errata applies.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/es/es_stratixv.pdf#page=2
The good news is that a fix part is available, your customer is reported as using:
5SGSED8N2F45I2L
But they must order parts with the full part number:
5SGSED8N2F45I2LCV
The *CV indicates fixed PCIe Gen2 silicon Hard Reset Controller.
Without fixed silicon, only Gen1 is supported in Stratix V.
Hope this clarified,
Regards,
Wincent_Intel
Regular ContributorHi,
1.Does stratix v gt support cvp with gen2?
- CvP is available for Gen1 and Gen2 configurations. Detail you may refer to Userguide at link below under Section10-2, Page 190/286
- https://www.intel.com/content/dam/support/us/en/programmable/support-resources/fpga-wiki/asset01/stratix-v-hard-ip-for-pcie.pdf
2.How can i set nperst pin assignment for pcie, that quartus put it in periph.jic image. Because as i right understanded KB, in periph image only hard pcie, my assignment with pull up resistor for pin not used... And thats why my periph image not start(pcie).
- You can refer to KnowledgeBase "How should I use the four dedicated PCI Express nPERST* pins on Stratix V devices?"
- https://www.intel.sg/content/www/xa/en/support/programmable/articles/000074772.html
Let me know if this is helpful.
Regards,
Wincent_Intel
Occasional ContributorAs for the first question and your answer user guide Stratix V support cvp on gen 2, but platform designer does not in Q 18.1 and 20.1. I will attach screenshot
