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Honored ContributorStratix IV Dev Board with Nios II Ethernet Standard Design: No PHY connected
I have an Altera Stratix IV 4sgx230 Development Board and using the NIOS II Ethernet Standard Design Example. I have found an issue where the PHY communication fails with the error “No PHY connected” IF the default demo code has NOT been run which configures the PHY. A workaround is included, however I would like to know if others can replicate this problem or suggest what is wrong. I find it hard to believe Altera did not notice this.
board: Altera 4sgx230 Development Board demo project instructions: using the nichestack tcp/ip stack – nios ii edition tutorial (https://www.altera.com/literature/tt/tt_nios2_tcpip.pdf) hardware design files: nios ii ethernet standard design example (https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-net-std-de.html) software design files: Built from Simple Socket Server App/BSP template in Quartus 13.0 quartus version: 13.0 By default this design works. This means the dev board is powered on and initially runs its demo code loaded in flash which includes a simple socket server. I can then load the .sof and run the software from NIOS. Everything works – or appears that way. The issue occurs if you do NOT run the demo code from flash which configures the PHY. Easy way to do this is change the SW2 rotary switch from ‘0’ to ‘1’. Alternatively you can wipe the flash. When the board is powered on, no design is loaded to the FPGA. In this case, the PHY fails to communicate: InterNiche Portable TCP/IP, v3.1 Copyright 1996-2008 by InterNiche Technologies. All rights reserved. prep_tse_mac 0 Your Ethernet MAC address is 00:07:ed:ff:af:a0 prepped 1 interface, initializing... [tse_mac_init] INFO : TSE MAC 0 found at address 0x0800a000 ERROR : MAC Group[0] - No PHY connected! INFO : PCS[0.0] - Configuring PCS operating mode INFO : PCS[0.0] - PCS SGMII mode enabled ERROR : PHY[0.0] - No PHY connected! Speed = 100, Duplex = Full OK, x=0, CMD_CONFIG=0x00000000 MAC post-initialization: CMD_CONFIG=0x04000203 [tse_sgdma_read_init] RX descriptor chain desc (1 depth) created mctest init called IP address of et1 : 0.0.0.0 Created "Inet main" task (Prio: 2) Created "clock tick" task (Prio: 3) DHCP timed out, going back to default IP address(es) Simple Socket Server starting up [sss_task] Simple Socket Server listening on port 30 Created "simple socket server" task (Prio: 4) The error line is: “No PHY connected”. Ignore the later DHCP errors which is a side effect of the PHY communication failure. I believe the PHY is already configured when the default Altera demo is started from flash. When the default demo is disabled, the PHY fails to init. I suspect this may go unnoticed by most people. Can anyone recreate this problem or suggest any fixes? I am guessing the issue is in Qsys. I don’t think I’m going to spend the time to SignalTap the MDIO bus to the PHY. Instead, my solution is to abandon this demo project and instead use the triple speed ethernet design example (https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-tse-sgdma.html). Any comments are welcome.
