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JELogan's avatar
JELogan
Icon for New Contributor rankNew Contributor
3 years ago

Stratix 10 I/O Maximum Frequency

For a particular design I have an external, 1 GHz, clock. An ideal solution would be to use this clock to clock some FPGA logic. I aim to use a 1:1 PLL clock to help improve timing and clock routing ...
AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

As we do not receive any response from you on the previous question/reply/answer that we have provided, please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.