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JELogan's avatar
JELogan
Icon for New Contributor rankNew Contributor
3 years ago

Stratix 10 I/O Maximum Frequency

For a particular design I have an external, 1 GHz, clock. An ideal solution would be to use this clock to clock some FPGA logic. I aim to use a 1:1 PLL clock to help improve timing and clock routing ...
AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Thank you for reaching out Intel FPGA Community.


According to this Knowledge Base article, refer here Will Altera publish the maximum I/O toggle rate specifications for... (intel.com), unfortunately we are not published the maximum IO toggle frequency in the datasheet for newer device anymore.


All of the standard supported I/O signaling frequencies is depended on design and also system customization form factors.


Therefore, the I/O toggle rate specifications was being removed from Stratix 10 device datasheet. The best options are using HSPICE or IBIS simulations.


Regards,

Aqid